Devices such as microwave field effect tranistors (FETs) are used in a variety of applications such as switching, amplification, attenuation, phase shifting, etc. These devices are controllable by logic level inputs of 0 and -5 volts. Often, such devices are interfaced with digital control circuitry employing transistor-transistor logic (TTL) or complementary metal oxide semiconductor (CMOS) logic. TTL logic levels are typically +3.6 and .0.V; and CMOS logic levels are typically +5 and 0 V. A TTL logic "0", however, may be as high as 1 V, and a TTL logic "1" V may be as low as 2 V. Thus there has been a need for a voltage translator designed to translate the range of TTL and/or CMOS logic levels to 0/-5 V levels in a single circuit.
Conventional prior art translators such as the CMOS to 0/-5 V level translator shown in FIG. 1 typically employ schottky diodes and MESFETS. These translators suffer from the problems of poor temperature and bias supply sensitivity, and excessive power dissipation. Poor bias supply sensitivity over temperature is due largely to the mismatch in temperature coefficients between the schottky diodes and MESFETS.
Ideally, the translator should be able to translate the input logic to the desired 0/-5 V outputs with bias supply voltages that are allowed to vary approximately .+-.20% over temperature or otherwise. Conventional translators such as that of FIG. 1 can generally come close to providing proper outputs with this bias supply Variation at room temperature. However, as the temperature varies over a moderate range, for example, from -10.degree. to +80.degree. C., proper circuit performance is provided only if the bias voltages remain at their nominal design value within about .+-.10%
Thus, at a nominal temperature such as room temperature, a conventional translator design takes into account presupposed I-V characteristics of the diodes, and Ids vs. Vds, Vgs curves of the MESFETS to arrive at an allowable bias voltage range of operation. Within this allowable range, the output logic levels fall into an established tolerance range to enable output logic states to be distinguished. Also, the outputs will change state when the input logic level reaches a predetermined switching voltage level. When the supply voltage varies to a value outside the allowable range, the output states will no longer change state in accordance with a change in the input logic state. As the temperature varies significantly off the nominal temperature, the I-V and Ids vs. Vds, Vgs curves undergo an incompatible change in characteristics such that the allowable bias voltage range of operation is narrowed substantially.
Another prior art drawback is excessive power consumption. Ideally, it would be desirable for an entire translator circuit to draw about 1 mA over a moderate temperature range of about -10.degree. C. to +80.degree. C. However, it is not uncommon for a conventional translator to draw 3 mA or more over this temperature range.
One major contributor to the power consumption is the inclusion of voltage divider network 18 as shown in FIG. 1 which generates an intermediate bias voltage Vss of about -3 V. The bias voltage Vss is essential to the operation of the prior art translator. A supply voltage Vcc of about +5 V is translated by the FET Q1 and the string of diodes D1 down to a potential close to the Vss potential at circuit node A. The input logic level at Vin is determinative of the potential at node A, and in turn, FET Q3 is turned ON or OFF, thereby impacting the state of FET Q4. Diodes D2 and FET Q2 then serve to control the voltage at circuit node B which is determinative of the complementary output states OUTA and OUTB. Another source of excessive power consumption is the buffer diode FET logic (BDFL) stage 19 preceding the output stage. The BDFL stage aids in the current driving capability of the translator. The intermediate supply voltage Vss is also coupled to this stage as well as to the inverter 14.
Another problem with conventional translator designs is that circuit performance with bias supply variation over a wide temperature range is degraded for designs that attempt to accommodate both TTL and CMOS input logic. For example, the circuit of FIG. 1. is optimized for CMOS input logic wherein a logic high is about 2.7 V, minimum. Accordingly, the circuit is designed to switch output states when the input logic level rises past a threshold of about 2.5 V. Over a moderate temperature range, such a circuit can operate with bias supply variation of about 10%. This translator may be redesigned to lower the switching threshold to about 1.8 V in order to accommodate TTL input logic, which may be as low as 2.0 V. In this case, however, a limited bias supply variation of substantially less than 10% can be tolerated over the temperature range. To achieve the same 10% bias supply tolerance range over temperature for a TTL translator, a separate design would be required which would be unable to also accommodate the higher CMOS input potentials.
Therefore, it is an object of the present invention to provide a temperature and bias supply insensitive level translator to translate input logic of either TTL or CMOS logic levels to 0/-5 V levels in a single circuit.
It is a further object of the present invention to provide a low power consumption level translator.